1. Field of the Invention
This disclosure relates to phase and delay locked loops, more particularly, to phase and delay locked loops having a charge pump, and semiconductor memory devices having phase delay locked loops.
2. Description of the Related Art
In conventional phase and delay locked loops using a charge pump, a single output charge pump supplies current from a supply constant current source to an output terminal in response to an up signal, and discharges current through a discharge constant current source from the output terminal in response to a down signal. However, even though the single output charge pump is designed such that the supply constant current source and the discharge constant current source have the same current amount, the supply constant current source and the discharge current source may differ from each other in actual operation.
In general, phase and delay locked loops attempt to make an input clock signal and an output clock signal identical in phase. When the phases of the two clock signals are approximately the same, the loop enters a locked state. Thereafter, an up signal and a down signal, adjusting the phase of the output clock signal, should be identical. However, since the supply current amount and the discharge current amount are often different in practice, the loop does not enter a locked state when the up signal and the down signal are identical, but enters a locked state when the up signal and the down signal have a pulse width or a phase difference.
The above-described phase and pulse width difference may occur in delay locked loops as well as phase locked loops.